When the thickness of a top silicon layer approaches 20 nm, a gate sidewall etching process produces a high density of voids in the silicon in the source/drain regions. This high density of voids degrades the performance of the device and production yield. This problem becomes more severe as the top silicon thickness is reduced, which is required in shorter channel length device fabrication.
Two techniques are known in the prior art for fabrication of ultra-thin SOI MOS transistors. The first technique requires nitride protection of a gate area and local oxidation of silicon (LOCOS) to provide a thin gate area. For ultra-thin SOI transistor fabricated by LOCOS, the thinned gate region has to be larger than the gate length by at least one alignment tolerance. The thickness of the sidewall oxide has to be larger than two alignment tolerances otherwise the silicon in this region will be completely removed during sidewall oxide etching, causing a disconnection between the source/drain regions and the channel region. However, the resistance of a thin or ultra-thin drain extension region, once formed by LOCOS, is too large for efficient use in high performance devices.
The second technique is used for conventional SO device fabrication and requires a raised source/drain process. Such a raised source/drain process requires a seed silicon layer Without such a seed silicon layer, selective growth of silicon cannot be accomplished. However, when the thickness of the top silicon is very thin, e.g., no thicker than 10 nm, all of the silicon in the source and drain region will be completely removed during any etching process for gate oxide sidewall formation. As a result, selective silicon growth cannot occur and the source/drain regions cannot be formed.